John Cockerill, enablers of opportunities
Driven since 1817 by the entrepreneurial spirit and thirst for innovation of its founder, the John Cockerill Group develops large-scale technological solutions to meet the needs of its time: facilitating access to low carbon energies, enabling sustainable industrial production, preserving natural resources, contributing to greener mobility, enhancing security and installing essential infrastructures.
Its offer to businesses, governments and communities consists of services and associated equipment for the sectors of energy, defence, industry, the environment, transports, and infrastructures. With more than 8,000 employees, John Cockerill achieved a turnover of € 1.417 billion in 2024 in 28 countries, on 5 continents.
John Cockerill has been providing its expertise to the defense industry for 200 years. Today, John Cockerill Defense offers Cockerill® modular gun turrets from 25 to 120 mm caliber, Arquus® high-mobility vehicles, technical and tactical training on these systems, and Agueris simulators.
Your Mission:
The goal of this internship is to develop a proof-of-concept of an IP which implements a BiSS through a AXI4 lite register interface. An existing SSI IP will be adapted to be able to deal with both SSI and BiSS protocols. The IP must be integrated into a Xilinx FPGA technology (e.g. zynq ultrascale+). The proof-of-concept shall be developed on a Xilinx development board.
1. Define the needs
You will start by understanding the SSI and BISS protocols, then the architecture and the integration of IPs in a Xilinx FPGA.
SSI:
BiSS:
2. Conceptual design
You will analyze the existing AXI4 Lite SSI IP.
You will define and evaluate the development boards and FPGA needs.
3. Design and test of an AXI4 lite BiSS IP
You will create an AXI4 lite with a BiSS interface IP. You will then validate the behavior of the IP using simulation testing tools (VHDL and/or UVM testbench) .
4. Software programming and HW tests
You will test the IP integrated in a small software project in real conditions on hardware. You must develop the software and access the stability and the performances of the design.
5. Merge of the BiSS IP into the SSI one
You will then merge the logic of the BiSS IP into the SSI one. You will have to adapt the register map of the SSI IP to integrate the developed IP.
You will also adapt its simulation tests and test the final IP on hardware.
Subject discussed:
- SSI, BiSS, AXI4-Lite
- C Software programmation
- Xilinx FPGA
- Vivado development tools
- VHDL
- Simulation testbench
Your Profile:
- Student in a master's degree education level in electronic
- Minimum level B2 in French and English
- Available for at least of 2-3 months
Your Internal Support:
During this internship, you will be supported by the electronic R&D department and the electronic industrialization and prototyping department of John Cockerill Defense. The internal supervisors will be:
- Matthieu Close (R&D engineer) – project definition
- Maxime Javaux (R&D engineer) – project definition
- Quentin Gaspart (R&D engineer) – FPGA design
What we offer you:
- Immersion in a stimulating, technology-driven environment
- Concrete and rewarding responsibilities
- A caring and passionate team
We look forward to receiving your application and meeting you.
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